1. Field of the Invention
The present disclosure generally relates to the field of semiconductor devices, and, more particularly, to metallization systems including sensitive low-k dielectric materials and ultra low-k (ULK) dielectric materials.
2. Description of the Related Art
Today's global market forces manufacturers of mass products to offer high quality products at a low price. It is thus important to improve yield and process efficiency to minimize production costs. This holds especially true in the field of semiconductor fabrication, since here it is essential to combine cutting edge technology with volume production techniques. One important aspect in realizing the above strategy is seen in continuously improving device quality with respect to performance and reliability, while also enhancing the diversity of functions of semiconductor devices. These advances are typically associated with a reduction of the dimensions of the individual circuit elements, such as transistors and the like. Due to the continuous shrinkage of critical feature sizes, at least in some stages of the overall manufacturing process, frequently new materials may have to be introduced so as to adapt device characteristics to the reduced feature sizes. One prominent example in this respect is the fabrication of sophisticated metallization systems of semiconductor devices in which advanced metal materials, such as copper, copper alloys and the like, are increasingly used in combination with low-k dielectric materials which are to be understood as dielectric materials having a dielectric constant of approximately 3.0 and less, wherein, in most recent developments, materials have been used in which the effective dielectric constant may be even further reduced, for instance, by providing a porous structure, wherein these materials may also be referred to as ultra low-k (ULK) dielectrics. By using highly conductive metals, such as copper, the reduced cross-sectional area of metal lines and vias may at least be partially compensated for by the increased conductivity of copper compared to, for instance, aluminum, which has been the metal of choice over the last decades, even for sophisticated integrated devices.
On the other hand, the introduction of copper into semiconductor manufacturing strategies may be associated with a plurality of problems, such as sensitivity of exposed copper surfaces with respect to reactive components, such as oxygen, fluorine and the like, the increased diffusion activity of copper in a plurality of materials typically used in semi-conductor devices, such as silicon, silicon dioxide, a plurality of low-k dielectric materials and the like, copper's characteristic of generating substantially no volatile byproducts on the basis of typically used plasma enhanced etch processes and the like. For these reasons, sophisticated inlaid or damascene process techniques have been developed in which typically the dielectric material may have to be patterned first in order to create trenches and/or via openings, which may then be coated by an appropriate barrier material followed by the deposition of the copper material. Consequently, a plurality of highly complex processes, such as the deposition of sophisticated material stacks for forming the interlayer dielectric material including low-k dielectrics and ULK materials, patterning the dielectric material, providing appropriate barrier and seed materials, filling in the copper material, removing any excess material and the like, may be required for forming sophisticated metallization systems, wherein the mutual interactions of these processes may be difficult to assess, in particular, as material compositions and process strategies may frequently change in view of further enhancing overall performance of the semiconductor devices.
For example, the continuous shrinkage of the critical dimensions may also require reduced dimensions of metal lines and vias formed in the metallization system of sophisticated semiconductor devices which may lead to closely spaced metal lines, which in turn may result in increased RC (resistive capacitive) time constants. These parasitic RC time constants may result in significant signal propagation delay, thereby limiting overall performance of the semiconductor device, although highly scaled transistor elements may be used in the device level. For this reason, the parasitic RC time constants may be reduced by using highly conductive metals, such as copper, in combination with dielectric materials of reduced permittivity, also referred to as ULK materials, as previously discussed. On the other hand, these materials may exhibit significant reduced mechanical and chemical stability, for instance when exposed to the various reactive etch atmospheres, for instance during etch processes, resist removal and the like, thereby increasingly creating a damage zone at the exposed surface portions of these sensitive dielectric materials. The damaged surface portions, however, may result in reduced reliability of the overall metallization system, that is, a premature device failure may occur during operation of the device and/or subsequent process steps may be significantly affected by the damaged surface portions, thereby also contributing to a reduced overall performance and reliability. Moreover, the damaged zones of ULK materials may have a significantly increased dielectric constant compared to the initial material due to the modification caused by the etch processes. For these reasons, in some conventional process strategies, the damaged surface portions may be removed prior to subsequent process steps, which may also be associated with certain negative effects on the finally obtained semiconductor device, as will be described in more detail with reference to FIGS. 1a-1c. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in an advanced manufacturing stage, i.e., in a manufacturing stage in which a metallization system 150 is to be formed on the basis of sensitive dielectric materials in combination with highly conductive metals. As illustrated, the semiconductor device 100 comprises a substrate 101, above which is formed a semiconductor layer 102, such as a silicon layer and the like, in and above which circuit elements 110 are typically provided, such as transistors, resistors, capacitors and the like. In sophisticated semiconductor devices, the circuit elements 110 may be formed on the basis of design rules requiring critical dimensions of 50 nm and significantly less, thereby enhancing performance of the individual circuit elements 110 and also providing a high packing density in and above the semiconductor layer 102. Consequently, an appropriate adaptation of the packing density in the metallization system 150 is required in order to appropriately connect the individual circuit elements 110 without consuming undue overall chip area and avoiding the necessity of providing a large number of individual metallization layers in the system 150. Typically, a plurality of metallization layers have to be implemented in the metallization system 150, wherein, for convenience, two adjacent metallization layers 120, 130 are illustrated in FIG. 1a. For example, the metallization layer 120 comprises an appropriate dielectric material 121, such as a low-k dielectric material, whose dielectric constant is 3.0 or significantly less. For example, as discussed above, in sophisticated cases, at least some of the metallization layers 120, 130 may comprise a ULK material having a dielectric constant of 2.7 or less, which is typically accomplished by providing a low-k dielectric base material and generating a porous structure in the dielectric base material, thereby further reducing the dielectric constant, however, thereby also reducing the mechanical and chemical resistivity of these sensitive materials, at least for specific reactive process atmospheres, which may typically have to be established upon forming the metallization system 150.
It should be appreciated that the dielectric constant of materials that are typically used in the metallization system 150 may be determined on the basis of well-established measurement procedures in which an appropriate material layer may be patterned into a capacitive structure having any desired configuration, wherein the material characteristics in terms of dielectric constant may then be determined by performing electrical measurement processes. In other cases, the material characteristics may be efficiently determined on the basis of sensitive analysis techniques, such as Fourier transformed infrared spectroscopy (FTIR), which is very sensitive to chemical modifications of materials and which may also allow a quantitative determination of materials within a material sample, wherein the material composition may then be efficiently correlated to a dielectric constant value, which may have been obtained by other measurement techniques. Consequently, the term low-k dielectric material may thus relate to a material having a dielectric constant of 3.0 and less based on well-established measurement techniques, wherein typically measurement results may vary by less than five percent. Similarly a ULK dielectric material may be considered throughout this application as a dielectric material having a dielectric constant of 2.8 and less, wherein typically the range of approximately five percent measurement tolerances have to be taken into consideration, depending on the measurement technique used for determining the dielectric constant. Furthermore, as discussed above, ULK materials may typically have a porous structure in which pores of dimensions of one to several nanometers may typically be randomly distributed across the entire material, wherein the material characteristics may nevertheless be considered as uniform, as long as a corresponding sample volume may be significantly greater than a corresponding “nano air gap” or pore, that is, as long as a plurality of nano pores may be provided within a sample volume. Furthermore, the metallization layer 120 may comprise a plurality of metal lines 122, which may provide the inner level electrical connection in the metallization layer 120. The metallization layer 120 may have a similar configuration as will be described with reference to the metallization layer 130. The metallization layer 130 may also comprise a low-k dielectric material 131 or a ULK material in the above-defined sense, in which a plurality of metal lines 132 are embedded. The metallization layer 130 may be considered as comprising a metal line layer 130B, the thickness of which may be substantially defined by the depth of the metal lines 132. Furthermore, a via layer 130A is typically provided so as to connect at least some of the metal lines 132 with some of the metal lines 122 of the lower lying metallization layer 120 at specific positions, as is, for instance, indicated by the dashed lines 132V. Consequently, the via layer 130A may be comprised of a portion of the dielectric material 131 in combination with one or more dielectric materials 133 having superior behavior with respect to chemical resistivity and mechanical stability. The layer 133 may also be considered as an etch stop layer and may be comprised of silicon nitride, nitrogen-containing silicon carbide, silicon dioxide or any appropriate combination of these materials in order to control the patterning process for forming corresponding openings of the vias 132V. Furthermore, in some cases, the etch stop layer 133 may also provide diffusion blocking abilities in order to avoid undue copper diffusion into sensitive device areas. To this end, typically, a significant amount of nitrogen may be incorporated in the layer 133.
The metal lines 132 may typically be comprised of a conductive barrier layer 132A or a layer system comprising two or more individual layers, while a highly conductive core metal or fill metal 132B may provide the desired superior conductivity of the metal lines 132 for a given cross-sectional area thereof. For example, copper or copper alloys may be provided for the metal 132B. Furthermore, as illustrated, the metal lines 132 may have to be provided in accordance with tightly set design rules in order to achieve the desired density of metal lines in the metallization layer 130. For example, as illustrated in FIG. 1a, a critical width 132W may be adjusted on the basis of design criteria, thereby also defining a pitch 132P, which may be of the same order of magnitude in densely packed device areas. For example, the dimensions 132W, 132P may be 100 nm and less in sophisticated semiconductor devices, depending on the metallization level considered.
As discussed above, the overall performance of the device 100 is strongly influenced by the performance of the metallization system 150, for instance in terms of signal propagation delay caused by parasitic RC time constants, which in turn are mainly affected by the parasitic capacitance of the metal line layers, such as the layer 130B. Consequently, it is extremely important to reduce the dielectric constant of the material 131 as much as possible, in particular in densely packed device areas, thereby requiring extremely low dielectric constant values for the material 131. Consequently, the presence of any modified material portions, as indicated by 131M, within the dielectric material 131 in the spaces between the closely spaced metal lines 132 may have a significant influence on the overall integrated dielectric constant and thus on the finally achieved electrical performance of the metallization system 150. In particular, very sensitive ULK materials may suffer from a significant material modification caused by exposure to reactive process atmospheres, thereby forming densified surface areas with a significantly increased dielectric constant, as is shown in FIG. 1a by the modified surface layers 131M which delineate at least the sidewalls of the metal lines 132.
Typically, the semiconductor device 100 as shown in FIG. 1a is formed on the basis of well-established process techniques which include the formation of the circuit elements 110 followed by an appropriate manufacturing sequence for providing a contact structure (not shown), which may act as an interface between the circuit elements 110 and the metallization system 150. Thereafter, the metallization system 150 may be formed by depositing an appropriate dielectric material, such as the materials 121 and 131 in combination with the etch stop layer 133. For convenience, corresponding manufacturing processes may be described with reference to the metallization layer 130, wherein it should be appreciated that similar process techniques may also be applied to the metallization layer 120 when requiring a similar configuration as the layer 130. Thus, after providing the metallization layer 120, the dielectric material 131 is deposited, for instance in the form of a silicon-containing material, which may exhibit a desired low dielectric constant which may be even further reduced on the basis of any appropriate treatments in order to form a porous structure and the like. In other cases, any other materials may be applied, for instance by spin-on techniques and the like, and any post-deposition treatments may be applied in order to further reduce the dielectric constant. At any rate, a wide class of ULK materials may suffer from a reduced mechanical and chemical resistivity in view of a plurality of plasma assisted etch recipes, cleaning processes and the like.
After providing the dielectric material 131 having the desired reduced dielectric constant, a complex patterning sequence is performed, for instance including the deposition of anti-reflective coating (ARC) materials in combination with resist materials so as to provide an appropriate etch mask in order to define the width 132W and the pitch 132P, as well as the lateral size and position of any vias 132V. The corresponding patterning sequence may represent a critical process sequence, since the lithography as well as the subsequent etch patterning strategies are designed so as to provide the smallest features sizes that may be consistently achieved in accordance with the specific design rules. Consequently, complex plasma assisted etch processes may have to be applied and subsequently any resist masks, hard mask materials and the like may have to be removed, thereby requiring performing a plurality of complex processes. Consequently, the material 131 within the resulting openings for the metal lines 132, and also for corresponding vias, may be repeatedly exposed to reactive atmospheres, which may result in a certain degree of damage, thereby forming the modified surface layer 131M. Due to the significantly different material characteristics of the modified layer 131M, the dielectric constant thereof may also be significantly increased, thereby, in total, increasing the parasitic time constants in the metal line layer 130B. Thereafter, the barrier material 132A may be formed, for instance, by well-established deposition techniques, followed by the deposition of the fill metal 132B, which may typically be accomplished on the basis of electrochemical deposition processes. Next, any excess material may be removed, for instance by chemical mechanical polishing (CMP), electro CMP, electro etching and the like, wherein also typically any modified portion of the dielectric material 131 may be removed from the top surface of the metallization layer 130.
Since the presence of the modified material 131M having the increased dielectric constant may result in reduced performance and thus increased power consumption of sophisticated semiconductor devices, such as complex microprocessors and the like, it has been proposed to remove the material 131M prior to forming the metal lines 132.
FIG. 1b schematically illustrates the semiconductor device 100 during a corresponding process strategy. As illustrated, trenches 134 are formed in the low-k dielectric material 131 on the basis of the critical width 132W, which may not be arbitrarily reduced due to the above-specified restrictions of the involved lithography and patterning processes. Thus, as illustrated, the modified material layer 131M may be formed within the openings 134, which may have significantly different material characteristics. Consequently, in some conventional approaches, the modified material layer 131M may be efficiently removed by using appropriate wet chemical etch recipes, as indicated by 103, which may exhibit a pronounced selectivity with respect to any non-modified portions of the dielectric material 131. For example, wet chemical chemistries based on HCL may be efficiently used for substantially selectively removing the modified portion 131M. For example, the layer 131M may have a thickness of approximately several nanometers to ten nanometers and more, which may thus be efficiently removed during the wet chemical etch process 103, without significantly affecting the non-modified portion 131, since the actual exposure time through the ambient 103 may be relatively short, while a moderately high degree of selectivity may also be observed.
FIG. 1c schematically illustrates the device 100 after the removal of the modified layer 131M, which, however, may result in an increase of the width of the trenches 134, as indicated by 134W. At the same time, the pitch 132P may be reduced, which may result in inferior process conditions upon filling the trenches of increased size 134 with the conductive materials. That is, the reduced pitch 132P may result in an increased probability of creating leakage paths between adjacent metal lines and/or the overall dielectric strength may be reduced, which may thus cause increased yield losses and reduced reliability of the metallization system 150. Thus, a corresponding shrinkage in the pitch 132P may have to be taken into consideration upon designing the semiconductor device 100, wherein, in combination with the increased width 134W, generally the resulting packing density in the metallization layer 130 has to be reduced.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.